I have finally put my foot down with how to proceed utilizing the FPGA with the wire wrap boards. I was hoping to build a hybrid system that would use the physical 6502, VIA, ACIA, 256k of RAM and clock/calendar chips, interfaced with the TinyFPGA handling the glue logic. But try as I might, I… Continue reading 1010 -The foot has spoken
1001 – Notes and Decisions
Another long gap in posts while I've mainly focused on coding for the FPGA. As previously mentioned, trying to synthesize each component of the /// from the schematics has helped me to learn how things work. As I've written and re-written different modules and poured over all sorts of datasheets, I've learned a lot about… Continue reading 1001 – Notes and Decisions
1000 – We’ve got Synced Video
Virtual synched video signal Here’s what I got on the first try. I’ve got the four digital “RGB” signals, the color burst and the SYNCH signals routed through a set of resistors to create analog color NTSC composite video as per the schematics. The good news is that it’s a nice, steady 60Hz non-interlaced picture.… Continue reading 1000 – We’ve got Synced Video
Status Report
What's taking so damn long? That's a good question. Turns out just accurately modeling a video state counter in Verilog is much harder than I'd thought. If you know anything about how the horizontal and vertical video states work in an Apple ///, you know it's not as simple as "count from 0 to the… Continue reading Status Report
0111 – Missing Parts
As I slowly near completion of my timing circuit board, I've been adding components to their sockets and testing the different signals they produce. The basic signals (14MHz, 7MHz, 3.5MHz, etc.) seem to be clocking correctly. Having the quartz oscillator socketed allows me to remove it and replace it with a simple 1kHz 555 timer-based… Continue reading 0111 – Missing Parts
0110 – Timing is everything
Before I get much further with the video module, I need to properly flesh out the heartbeat of the system: the timing circuit. As mentioned previously, the /// uses a 14.318MHz clock. The reason for such a high frequency is that (apart from other components in the system) the video module needs synchronized clocks at… Continue reading 0110 – Timing is everything
0101 – Video output
Now that I've completed a basic 6502-based computer, my next milestone is to implement a video output system. The Apple ///'s video system was unique, in that it provided similar video modes to the Apple II, as well as additional modes to display higher resolutions with many more colors. Additionally, unlike the II which was… Continue reading 0101 – Video output
0100 -Milestone 1: a running program
Today marks the completion of my first milestone: running a program in ROM and keyboard input/ display output through the ACIA to USB-serial bridge. A happy day to say the very least. Another "Hello World" of a fully-functioning computer. Once wire wrap was completed (and failed, then troubleshot, rewrapped, repeat...), I began the task of… Continue reading 0100 -Milestone 1: a running program
0011 – RAM and I/O
Getting to the free-run stage is easy. Where it gets complicated is when you add hardware to make your fancy program counter into a real computer. When you're doing a project like this, its assumed you are willing to put in the time to learn some electronics in order to move forward. Both the journey… Continue reading 0011 – RAM and I/O
0010 – Free Run and Hex Display
The first test of every new microprocessor "single-board" project is free-run. Once the CPU, clock, and reset circuitry is in place, we hardwire the data bus to supply the data pins on the 6502 with its opcode NOP (No-Operation). The hexadecimal for the NOP instruction is $EA. This is a simple do-nothing opcode that basically… Continue reading 0010 – Free Run and Hex Display
