Status Report

What's taking so damn long? That's a good question. Turns out modeling a video state counter in Verilog is much harder than I'd thought. I'm probably making it harder than it needs to be. But when you don't have a timing chart to compare against, and are just working with the description in the Clocks… Continue reading Status Report

0111 – Missing Parts

As I slowly near completion of my timing circuit board, I've been adding components to their sockets and testing the different signals they produce. The basic signals (14MHz, 7MHz, 3.5MHz, etc.) seem to be clocking correctly. Having the quartz oscillator socketed allows me to remove it and replace it with a simple 1kHz 555 timer-based… Continue reading 0111 – Missing Parts